In making silicon integrated circuits, many process steps require selective doping of a silicon substrate with high concentrations of p and n-doping material, such as boron and arsenic. Additionally, it is necessary to control the depth of penetration of the dopant. Ion implantation is the dominant technique in use today to achieve dopant profiles of high peak concentration and shallow depth. However, the implantation process, by its nature, damages the semiconductor substrate. This implantation damage has proven to be a performance and yield-limiting factor in silicon ICs and is a serious problem which influences the choice of a particular silicon IC fabrication process. In addition, ion implantation cannot be easily used in some non-planar processes, for example, to dope the sidewalls of trenches. To avoid implant damage and satisfy nonplanar doping requirements, various techniques have been proposed to outdiffuse the dopant from some grown or deposited material into a wafer of semiconducting material such as silicon. These processes typically suffer from one or more of the following problems, they are not highly reproducible, they are not clean and they do not introduce a high enough surface concentration of dopant, the source is eventually depleted.
There are numerous known methods for diffusing n-dopants into semiconductor wafers.
W. Runyan in "Silicon Semiconductor Technology", McGraw Hill, N.Y., 1965, describes arsenic diffusion using a solid source is usually performed from the reaction of arsenic trioxide and silicon. Vapors of the oxide are transported into the diffusion zone of a diffusion furnace by a mixture of nitrogen and .ltoreq.0.5% oxygen. The oxygen is added to prevent staining caused by the formation of an arsenic layer at the oxide-silicon interface. Surface concentrations obtained by this technique do not exceed (2-3).times.10.sup.19 cm.sup.-3, because of rapid depletion of the arsenic by evaporation from the silicon surface.
S. K. Gandhi, in "VLSI Fabrication Principles", John Wiley & Sons, 1983, pp 170-171 describes the use of spin-on dopants have with arsenic which consists of the arseno-siloxanes in an appropriate organic binder. Upon bake out at 250.degree. C., these react to form an arsenosilicate glass which acts as the source of this dopant. Higher doping concentration can be achieved by this method, since the glass serves as an evaporation barrier to the arsenic during diffusion. However, this process is inherently dirty because of the organic materials and glasses used, and is not suitable for the state-of-the-art semiconductor IC fabrication.
S. K. Gandhi, in "VLSI Fabrication Principles", John Wiley & Sons, 1983, pp 170-171 describes the use of sealed-tube technology has also been used successfully for arsenic diffusion. Here silicon slices and a solid arsenic source are sealed in a evacuated quartz tube. The arsenic source is typically silicon powder doped with arsenic to a concentration of about 3%. Surface concentrations of as high as 10.sup.21 cm.sup.-3 are achieved. However, the requirements of a sealed tube and limited source of As make the technique unsuitable for high volume silicon IC fabrication.
Y. W. Hsueh, J. Electrochemical Society, Vol. 6, 361-65, 1968 describes gaseous systems using arsine for arsenic diffusion into silicon. The diffusion was conducted in the temperature range of 1164.degree.-1280.degree. C. When hydrogen or nitrogen was used as the carrier gas, heavy pitting of the silicon surface was observed. This resulted in nonuniform and erratic sheet resistance on a silicon wafer. In order to avoid the pitting, a small amount of oxygen was mixed with arsine for arsenic diffusion. Although, the pitting was reduced, surface concentrations of only .ltoreq.2.times.10.sup.19 cm.sup.-3 were achieved.
In U.S. Pat. No. 3,812,519, to Nakamura et al. also utilized silicon doping via a gaseous source. In their experiments, a silicon semiconductor device is double doped with phosphorus and arsenic or boron and arsenic wherein the arsenic is present in an amount 3 to 40% of the other dopant. The method of the Nakamura et al. requires that, to achieve a high doping concentration, more than one species be added to the silicon semiconductor device.
Ion implantation, which is the presently used method to achieve very high doping levels, is unidirectional. Therefore, using ion implantation it is difficult to dope the sidewall of a trench.
The article entitled "Doping of Trench Capacitors by Rapid Thermal Diffusion", W. Zagozdzon-Wosik et al., IEEE, Electron Device Letters, Vol. 12, 264 (1991) shows doping of trench sidewalls. According to the method of this article, a doped glass is first spun onto a separate wafer. Then the wafer to be doped is placed in proximity to the glass-doped wafer and heated to allow evaporation of As-containing gas. This is simply a variation of other solid source techniques experimented with in the past. Their drawbacks are: the solid source is eventually depleted; the doping is sensitive to the spacing between the wafers and the source; they are not particularly clean; and one solid source is required for each wafer to be doped, which decreases throughput.
The article entitled "Laser Doping of Semiconductors" in "Laser Processes for Microelectronics Applications", 1988 (Electrochemical Society, Pennington, N.J., 1988), T. W. Sigmon describes a method requiring melting the silicon at the surface with a laser in order to incorporate As from AsH.sub.3 gas. The level and depth of As incorporation are determined by a variety of parameters related to the laser optics and laser operating conditions. The technique requires selective melting of the silicon in the area where the dopant is too be incorporated, and scanning across the wafer incrementally since the beam size is much smaller than the wafer diameter.